Regulator for controlling capacitor charge to provide complex waveform

ABSTRACT

In fuel injection ignition systems, it is necessary to provide control of the open time of the fuel injector valves which varies with the engine speed. However, for efficient operation with a minimum of pollution, the relationsip of valve open time to engine speed is not a simple relationship, and factors other than engine speed are involved. It has been found that the open time should change with engine speed by steps not directly related to engine speed. This can be accomplished by providing a waveform which varies with time across a capacitor by a regulator system which controls both increase and decrease of the voltage across the capacitor. This voltage waveform, which varies with time and is independent of engine speed, can then be combined with a ramp voltage initiated at a particular point of rotation of the engine at the time the injector valves are opened. The valves can then be turned off when the combined voltage has the desired relation to a voltage produced by manifold pressure to provide the required open time for the injector valves.

United States Davis et a].

atent 1 1 REGULATOR FOR CONTROLLING CAPACITOR C 1' GE TO PROVIDE COMPLEXWAVEFORM Filed:

Assignee:

Motorola,.lnc., Franklin Park, lll. Oct. 15, 1971 Appl. No.: 189,630

[ Apr. 10, 1973 Primary ExaminerJohn Zazworsky Attorney-Foorman L.Mueller et al.

[ ABSTRACT In fuel injection ignition systems, it is necessary toprovide control of the open time of the fuel injector valves whichvaries with the engine speed. However, for efficient operation with aminimum of pollution, the relationsip of valve open time to engine speedis not a simple relationship, and factors other than engine speed. areinvolved. It has been found that the open time should change with enginespeed by steps TO SWITCH 50 US. Cl. ..307/260, 123/32 EA, 307/229, notdirectly related to engine speed. This can be ac- 8, 320/1 complished byproviding a waveform which varies [51] Int. Cl... 4/02, HO3k 4/12 withtime across a capacitor by a regulator system Field f Search 312 9,which controls both increase and decrease of the volt- 2 2 age acrossthe capacitor. This voltage waveform, 143 which varies with time and isindependent of engine speed, can then be combined with a ramp voltageinkefel'fllces Cited itiated at a particular point of rotation of theengine at the time the injector valves are opened. The valves UNITEDSTATES PATENTS can then be turned off when the combined voltage has2,920,217 1/1960 House ..l.....307/260 X the desired relation to avoltage produced by manifold 3,430,073 2/1969 Leonard... ..307/260pressure to provide the required open time for the in- Chandos X valves3,643,180 2/1972 Shimamuya ..307/229 X I 17 Claims, 3 Drawing Figures VREG.

38 O 1 P 51 B3 F 3 REG.

. v 52 3| 33 4 r I T 35 2 32 B4 132 DISCH. CUR-RENT REG CKT. sol/RC5 F4: 45-

B4 44 8 I v 2 REG. CURRENT 7 SOURCE COMPARATOR To SWITCH 45 CKTI 2 24,07 (TURN OFF) h g i 6| 563 (L56 2? TIMING I FLOP CKT To SWITCH TOSWITCH (TURN ON) PATENTEBAPM 0197s SHEET 1 [IF 2 -SWITCH 45 CLOSED REG.

REG.

FLIP

FLOP

TO SWITCH 35 "TO SWITCH 45 (TURN ON) DISCH.

45-FT l 7 'L CURRENT CUR-RENT SOURCE SOURCE TO SWITCH 45 (TURN OFF) QDMPARATOR CKT.

PATENTH] APR 1 01973 SHEET 2 OF 2 Fxo $2.2;

.rZMwEDU mQmDOm 0 Nu h EMEEG mum Dow L1 .xu LED 1 REGULATOR FORCONTROLLING CAPACITOR CHARGE TO PROVIDE COMPLEX WAVEFORM BACKGROUND OFTHE INVENTION perature, and other conditions of the environment. Ex-

periments have shown that there is no simple mathematical relationshipof the 'valve open time with respect to engine speed. However, it hasbeen determined that satisfactory operation is obtained if the open timeof the valve is changed for different portions of the speed range withinthe wide range'of, operating speeds which may be used. Toprovidethe-chang es in open timefor the various speeds requires arelatively complex control system which tends to be expensive.

SUMMARY OF THE INVENTION It is an object of the present invention toprovide a system for preciselycontrolling the open time of the injectorvalves in a fuel injection system for maximizing the efficiency thereof.

It is another object of the present invention to provide precise controlof the opening and closing of the fuel injector valves for an enginewhich operates over a wide range of engine speeds, which has an accuracywithin one percent overa temperature range of from 50t0 +l35F.

Another object of the presentinvention is to provide a control forcharging a capacitor for providing a voltage waveform thereacross whichincreases and decreases with respect to time, which includes regulatorsfor precisely controlling the voltage during various time periods. 3

In an eight cylinder engine, two banks of four fuel injector valves eachmay be utilized to supply fuel to the cylinders. The time during which abank of injector valves is opened controls the amount of fuelsuppliedand should be varied with the speed of the engine. The presentinvention utilizes an electronic circuit, primarily an IC chip, toswitch between the two banks of injector valves and to control the timeduring which a bank of injector valves is open. The circuit includes astorage capacitor foreach bankof valves, and transistorized regulatingcircuits to change the voltage across the capacitor, with the circuitsproviding different voltages at different points in-time. During oneperiod of rotation of the engine, which is the exhaust stroke, thecapacitor is charged to provide thereacross a complex voltage waveformwhich varies with time, but is independent of the speed of rotation. Thecapacitor is then charged to provide a ramp operating voltage startingat the time the engine has completed the exhaust stroke. This ramp,which is developed during the following period of rotation, which is thepower stroke of the engine starts at a voltage which depends on thevoltage across the capacitor at the time the power stroke starts.

' The injector valves are opened at the time the ramp operating voltageis initiated, which is at a defined point of rotation. The valves willremain open until the voltage across the capacitor produced by thewaveform with the ramp operating voltage added thereto has apredetermined relation to a voltage responsive to manifold pressure inthe engine. Consequently, the

voltage of the waveform, which depends upon time,

0 will control the length of time during which the injector productionof the ramp operating voltage thereacross,

which also occurs alternately across each capacitor.

Since the ramp operating voltage is applied at a time dependent upon therotation of the engine, and the waveform is independent of the rotationof the engine, the ramp will be initiated at various different points onthe waveform, depending upon engine speed. When the ramp operatingvoltage is initiated, the production of the waveform across thecapacitor is terminated and the remainder of the waveform will not beproduced.

I BRIEF. DESCRIPTION OF THE DRAWINGS FIG. 1 shows the waveform which isdeveloped by the regulator circuit of the invention;

FIG. 2 is a block diagram of the regulator system of Q the invention;and

FIG. 3 is a circuit diagram of the system illustrated in FIG-2.

DETAILED DESCRIPTION FIG. 1 illustrates a wave shape which is desirablefor use in properly controlling the time during which the injectorvalves are open in a fuel injection system. The waveform shownrepresents the voltage across a capacitor which is used as the startingvoltage of an operating voltage ramp developed across the capacitor. Thefuel injector valves are open at the time the ramp starts, and the rampvoltage is compared with a voltage resulting from manifold pressure,and/or other engine characteristics to turn off the valves at the propertime.

The waveform in FIG. 1 has a first constant voltage portion 10 duringwhich a voltage 81 is provided across the capacitor, which lasts for ashort period, such as 3 milliseconds. At the end of this period, at timeG1, a down ramp 12 reduces the voltage across the capacitor to a lowervalue B2, to provide a second lower constant voltage portion 14 of thewaveform. This portion continues until the time G2, which may be about20 milliseconds after the start time. At this time an up ramp 16 isinitiated which continues until the voltage B3 is reached. This voltageis held until the time G3 to provide the third fixed voltage portion ofthe waveform, indicated as 18. The time G3 may be of the order of ,60milliseconds after the start time. At time G3, a second down ramp isprovided, indicated on the waveform as 20. This extends for a longerperiod and drops to a lower value B4, to provide the fourth fixedvoltage portion, which is indicated at 22.

The voltage values and time durations shown in FIG. 1, and which havebeen described, are independent of the speed of rotation of the engine.The particular values of voltage and time can be selected as may berequired for a particular application and the system can be used to.produce a waveshape different from that provide the waveform shown, andat a further point in the rotation an up ramp.25 is developed across thecapacitor. This may occur at any time after about 3 milliseconds afterstart of the rotation period, depending upon the speed of the engine;The ramp 25 is illustrated as starting shortly after the time 61, aswould occur during extremely high speed operation. A second ramp 25a(dashedline) is shown which represents operation at some intermediatespeed, and the ramp 25b (dot circuit for producing the waveform isdisconnected from the capacitor so that the waveform generation isterminated. If the ramp 25 starts during the portion 12 v of thewaveform, the remainder of the waveform is not generated. At the startof the ramp 25 ,a new waveform is generated on the second capacitor toproduce the same voltages at the times G1, G2 and G3, as will be ex- Iplained.

In FIG. 2 there is shown schematically the system of the invention forproviding the waveform illustrated in FIG. l across a capacitor 30.Four-voltage dividers 31,

32, 33 and 34 are-shown for providing the voltages B1, B2, B3 and B4,respectively. The alternate cycles are triggered'by switches 26.and 27which control the flipflopcircuit 28. The switches may be coupled to thedistrlbutor shaft of theengine and be operated at the and l 80 positionsof this shaft, respectively. As the distributor shaft rotates through180 for each full revolution of the crankshaft, the crankshaft rotatesthrough a full revolution between switch operations. The revolution 7following the operation of one switch 26 is the power'stroke for somecylinders, and the revolution following the operation of the next switch27 is the exhaust stroke for these cylinders.

At the startof the cycle providing the exhaust stroke, capacitor 30 willbe charged to a high value by current The capacitor 30 will be held atthe B1 level untilthe timing circuit provides a control at terminal G1representing the time G1 in FIG. 1. At time G1, the control from thetiming circuit 40 applied toregulator 38.will remove the control fromvoltage B1, and control is transferred to regulator 42 to providecontrol from the B2 reference. The discharge circuit 36 is alsoactivated by the regulator 38 at time G1 and causes the voltage acrossthe capacitor 30 to reduce to provide the down ramp 12, until thevoltage B2 is reached. The discharge current is then satisfied bycurrent from the B2 regulator allowing no more current to be drawn fromthe'capacitor. The voltage is then held at the fixed voltage B2 formingthe portion 14 of the waveform.

The B2 voltage continues until time G2, at which time the timing-circuit40 applies a potential to regulator 38 to cause the same to operate fromthe B3 'voltthe capacitor 30; The voltage across the capacitor 30increases as a result of the charging current from current source 44 toprovide the ramp 16, until the B3 voltage is reached. At this time theregulator 38 will cause the discharge circuit 36 to operate so thatcurrent which is supplied by the source 44 is shunted from applied bysource 52 through switch 50, which produced the ramp 25 during thepreceding cycle. At

the beginning of the cycle, switch 35 is closed to con nect dischargecircuit 36 to the capacitor 30, and switch 50 is opened to disconnectcurrent source 52. In addition, switch 45 is closed to connect currentsource 44 to capacitor 30. The operation of the switches 35, 45.and 50is controlled by the flip-flop 28. The capacitor 30 will initiallydischarge (since the discharge current is greater than the current fromcurrent source 44) until it reaches the B1 voltage level under controlof the B1, B3 voltage regulator 38. This regulator initially responds tothe voltagedivider 31 to hold the charge on capacitor 30'accurately atthe. B1 level by shuntingthe source current from circuit 44 through thedischarge circuit 36, allowing zero current to be drawn out of thecapacitor. r

capacitor 30, and capacitor 30is held precisely at the fixed B3voltageun'til the time G3.

' At the time G3, the timing circuit 40 applies a potential to theswitch 45 to disconnect the current source 44 so that current is nolonger supplied to the'capacitor 30 thereby. This control potential isalso applied to regula tor 46 t which causes the discharge circuit 36 todischarge capacitor 30 and provide the down ramp 20.- Thiscontinues'until the voltage drops to the B4 level, at which point theregulator 46 operates to hold. the capacitor 30 accurately atthis'level. Regulator 46 will precisely control the discharge circuit 36so that no current is drawn from capacitor 3.0. t

As previously stated, capacitor 30 is charged to provide an operatingramp at some time during the production" of. the waveform thereacross,depending upon the speed of the engine. The flip-flop 28 actuatesswitches 35 and 45 and applies a reset signal to the timing circuit 40when the engine is at one point to initiate the waveform-acrosscapacitor 30, and at the next point in the engine operation operatesswitch 50 to initiate the ramp. That is, switches 35 and 45 are opened,and switch 50 is closed to connect the current source 52 to thecapacitor 30 to apply current to the same to provide the ,ramp which isillustrated as 25 in FIG. 1. As previously stated, this may occur at anypoint along the waveform after 3 milliseconds. The voltage acrosscapacitor 30 may be applied to a comparator circuit 55 which'comparesthis voltage with a voltage from the engine applied at terminal 56, suchas a voltage related to manifold pressure. At the next engine position,all

switches change state to produce the waveform of FIG.

1 as previously explained.

At each time when switch 26 or 27 is operated, the timing circuit 40will be reset to start a new series of time periods Gl, G2, and G3. Aswill be explained,- the waveform generating circuitry will be switchedto another capacitor at the time that the operating ramp is applied tothe capacitor 30. Accordingly, the regulators will not be operative toeffect the voltage across capacihalf of the injector valves are open.During this operating period for the one capacitor, the second capacitoris being charged so that the waveform shown in FIG. 1

is developed thereacross. The capacitor C1 will be designated byreference numeral 60, and capacitor C2 will be designated by referencenumeral 62 The cycle will be described for developing the waveformacross capacitor 60, and the cycle for the other capacitor 62 is thesame but with the waveform and operating parts at alternate timeperiods.

' Switches 64 and 65 shown in FIG. 3 maybe reed A switches coupled tothe engine to operate at alternate and 180 rotation points of thedistributorshaft (full revolutions of the crankshaft). These may providemomentary contacts and are coupled to flip-flop circuit 66 which servesas a memory to record which switch was last operated. Circuit 66produces anoutput which will have one value during one revolution of theengine and a different value during the following revolution. The

dicated as 25 in FIG. 1. This is started at each change in the output ofthe flip-flop 66, and is alternately applied to the two capacitors 60and 62. The current source 76 includes switching means for controllingthe output to alternately apply the current to conductor 77 connected tocapacitor 60, and to conductor 78 connected to capacitor 62, dependentupon the state of the flipflop 66.

At the time the differential circuit 70 is operated to provide aconnection to capacitor60 (or capacitor 62), this capacitor is at itslargest value of voltage, since during the previous half cycle it hasbeen charged to produce the operating ramp 25. At this same time,current source 81 is connected to supply current to the capacitorconnected to the differential transistor 72 or 73 which is conducting.This control of the current source. 81 is also supplied by the flip-flop66. When transistor 72 is rendered conducting, this transistor completesa circuit from capacitor 60 to the collector of transistors 75 and 98which are connected in parallel. The transistors 75 and 98 are neversimultaneously connected between the regulated voltage and groundflip-flop 66 controls differential circuit 70 which seiectively renderstransistors 72 and 73 conducting. Transistor 72 has its collectorelectrode connected to the high potential side of capacitor 60 and itsemitter electrode connected through current source transistor 75 to thereference potential. Transistor 73 is connected in the same way tocapacitor 62.

A reference potential is provided for the differential circuit 70 by thevoltage divider including resistors 67 and 68, and diode 69, which areconnected-from the;

collector of the current source transistor 84 to ground. The voltagefrom the flip-flop 66 is applied'against the reference voltage providedby the divider, so that the differential circuit 70 switches as thevalue of the output of flip-flop 66 changes from one level to another.

The current source transistor 84 is illustrated inthe diagram as threetransistors 84, 84a and 84b, with the emitter and base electrodes tiedtogether. This can ac tually be a single transistor structure with asingle base and emitter, and with a plurality of collectors. Theconductivity of the transistor 84 is controlled by the current flowthrough resistors 67 and 68, by action of transistor 79. 1

The flip-flop circuit 66 is also connected to the current source 76, thecurrent source 81, and the timing circuit 80. The timing circuit 80produces three time periods G1, G2 and G3, which are initiated at eachchange in the output from the flip-flop 66 corresponding to eachoperation of switch 64 and of switch 65. As previously stated, the timeperiods G1, G2 andG3 are independent of the engine operation, and thesequence is started at each 180 rotation point of the distributor shaft.

The output of the flip-flop 66 which is connected to 'thecurrent source76 controls the operating ramp inestablishes the voltage B1 to which thecapacitor 60 is i to be initially charged. This voltage renderstransistor 85 conducting to apply the, voltage to the base of transistor86 which cooperates with transistor 87 to form a differential amplifier.Capacitor 60 is connected to the differential amplifier transistor 87 bytransistor 89. Since the capacitor 60 is at a high voltage, transistor86 of the'differential amplifier will be fully conducting to providecurrent from the collector 90 of source transistor 84a. This currentwill flow mainly through conductor 91 to render transistor 92conducting-Transistor 94, which is connected in series with transistor86 to ground, will be controlled by the current through. diode 95connected in series with transistor- 87 to ground.'As trarisistor 87 iscut off by the voltage from capacitor, 60, little or no current flowsthrough diode, 95, and this will cut off transistor 94, so that thecurrent from transistor 86 will flow through transistor 92; Transistor92 acts to render transistor 98 highly conducting to provide a path fordischarge of the capacitor 60 through transistor 72.

Capacitor 60 will, therefore, discharge rapidly and when it reaches thevoltage Bl, it will result in the balancing of the differentialamplifier including transistors 86 and 87, to thereby reduce theconduction of transistors 92 and 98 to effectively open the dischargepath. In the event that the capacitor 60 discharges below the value B1,this will render transistor 87 of the differential amplifier conductingsuch that it causes diode 95 to conduct, as well as transistor 94. Thiseliminates the drive to the base of transistor 92, which in turnterminates conduction of transistor 98. As a result, the chargingcurrent which is being supplied by current source 81 raises the voltageon the capacitor 60 to the B1 potential. Accordingly,

the regulator including differential amplifier 86, 87 and the voltagedivider 82, 83, in cooperation with the current source 81, controls thevoltage on capacitor 60 to hold the same at the B1 level.

At time G1, the timing circuit 80 applies a current from terminalGlthrough diode 99 to ground. This causes transistor 100' to conductcollector current of the same value as that from the G1 terminal. Thiswill turn on transistor 101 which, in turn, renders transistor 102conducting. Transistor 102 forms a current source andhas threecollectors designated 104, 105 and 106. Collector 104 is connected tothe base of transistor 101 to provide feedback action such that thecollector current-of transistor 100 is. approximately the same as thec'urrentin collector 104. In addition, the currents in collectors 105and 106 of transistor 102 are identical to that in. collector 104.Collector 105 is connected to the zener diode 108, connected between thebase of transistor 110 andground. Whentransistor 102 conducts, thissupplies current to the zener diode which renders transistor 110conducting. This lifts the voltage applied to the base of transistor 85to a high value so the transistor 85 has no control of the differentialamplifier 86, 87. This terminates the control from the B1 voltagedivider.

The collector 106 of transistor 102 is connected to the emitter oftransistor 112 and when transistor 102 is rendered conducting at timeG1, this also renders transistor 1 12 conducting. The base of transistor1-12 is connected tothe voltage divider including resistors 113 and 114,which are connected from the regulated voltage to ground. This dividerprovides the B2 voltage level, which is-coupled to the base oftransistor 112.

The'emitter of transistor 112 is also connected to the bases ofethitterbfollowet transistors 116 and 11.7, which are in turn connectedto the capacitors 60 and 62, respectively. Connected in the collectorcircuit of transistor 112-is a diode 118 in series with resistor 119.The voltage across diode 118 and resistor 119 is ap' plied throughconductorv 120 to the ,base of transistor 122 Transistor 122 is in acircuit for controlling transistor 75-which is connected in series withtransistor 72 to capacitor 60. The. collector current of transistor 122,which is determined by the ratio of resistor 119 to resistor 123,

controls the conductivity of transistor 124, which is a PNP transistorand has its base connected to the emitter of NPN transistor 125. Thiscollector current must be greater than the current from collector 109 oftransistor 84b to insure conduction of transistors 124 and 125. Thevoltage divider string including resistors 126, 127 and 1'28 applies aregulated potential to the base of transistor 125 which may have a valueof about 3 volts. When transistor 122 is conducting, it supplies basecurrent to transistor 124 to render the same conducting 'in accordancewith the potential applied-to its base from transistor 125. transistor124 completes a path through resistor 1'29 and diode 130 to provide apotential across diode 130 which is applied to the base of .transistor75'. This renders transistor 75 conductive to complete a discharge pathfor capacitor 60.

The value of the current in the collector of transistor 72 is determinedby the voltage across resistor 129 and the resistance value itself. Thevoltage across this resistor is essentially the same as the voltage atthe base of transistor 125, since the base-emitter voltage drop oftransistor 125, cancels the base-emitter voltage drop of In the eventthat capacitor 60 discharges below the B2 value, emitter followertransistor 117 will be rendered more conducting to supply current fromthe 13+ supply to force the capacitor back to the B2 value. Ac-' cordingly, transistor 117 in cooperation with transistor 112 and the voltagedivider acts as a regulator to hold the voltage across capacitor 60 atthe B2 level, which continues until time G2 as represented by level 14in FIG. 1.

At the time G2, a current is applied from terminal G2 of timing circuitto the base of transistor 135. Transistor 135 will conduct to rendertransistor 136 conducting to turn off transistor 138. At this point itis noted that transistor 138 is normally conducting since current issupplied from a collector of current source transistor84b to the zenerdiode 139. This zener diode develops a voltage which is applied to thebase of transistor 138 to render the same conducting and lift thevoltage applied to the base of transistor 140 to a high value.Accordingly, transistor 140 is normally at a value such that it has noeffect on the differential amplifier formed by transistors 86 and 87when transistor is not conducting. When transistor 138 is cut off, thevoltage divider formed by resistors 142 and 143 connected between theregulated voltage and ground now controls the voltage applied to thebase of transistor 140. I I

The B3 voltage from the voltage divider 142, 143 at the base oftransistor 140 now controls the differential amplifier 86, 87 which isagain coupled to the capacitor 60 by transistor 89 (and to capacitor 62by transistor 88), as previously described. In view of thef fact thattransistor is also conducting, its collector current satisfies thecurrent out of collector 106 of transistor 102 and pulls the voltage atthe emitter of transistor 112 down such that transistors 112, 117, and116 will not'conduct. Accordingly, the B2 voltage no longer controls thevoltage across the capacitor 60. In addition, the current through diode118 is reduced to zero and as a result, the collector current oftransistor 122 is reduced to zero; Current from collector 109 oftransistor 84b now flows through diode 133, which forces a reverse biason the base-emitter junction of transistor 124. This causes transistor124 to turn to off to turn off transistor 75, terminating the currentthrough the collector of transistor 72. The current through diode 133passes to ground through transistor 132 so that transistors 131, 132,and diode 133 clamp the voltage at the base of transistor 124 to threebaseemitter drops above the voltage at the junction of resistors 127 and128. This prevents the collector 109 from saturating, which would causedetrimental effects to the remaining circuitry. v

In the absence of collector current from transistor 72, the currentsource 81 provides current to capacitor 60 (or 62) to charge the samestarting at time G2 to produce the up ramp portion 16 of the waveformshown in FIG. 1. As previously stated, the current source 81 is alsoconnected to the flip-flop circuit 66 so that it applies current only tothe capacitor on which the waveform is being developed, which iscapacitor 60 in the operation being described; The current source 81 canbe set, in known manner, to 'chargecapacitor 60 to provide the desiredslope of the ramp portion 16. The current source 81 continues operatingduring'the period from the beginning of thewaveform generation to timeG3, arid 'is turned off at time G3 by the connection from the G3 outputof the timing circuit 80.

When the voltage across capacitor 60 reaches the B3 voltage level, thedifferential amplifier 86, 87 will become balanced. As the voltageacross capacitor 60 tends to rise above the B3 level, transistor 86 willbe rendered conducting to apply current through conductor 91 totransistor .92 which turns on transistor 98, as previously described.This provides a path for shunting the current from source 81 applied tocapacitor 60 through transistors 72 and 98. Accordingly, although thecurrent source 81 continues to supply current to the capacitor 60through the entire period from. time G2 to G3, when the B3 voltage levelis reached across capacitor 60, the current path is completed throughtransistors 72 and 98 to conduct the charging current so that capacitor60 remains at theB3 voltage level, receiving no more charging current.This produces the fixed voltage portion 18 of the waveform shown inFIG. 1. As previously stated, the-regulator including the differentialamplifier 86, 87 and'the voltage reference 142, 143 controls the voltageacross capacitor 60 to hold the same precisely at the desired B3 voltagelevel.

The voltage across capacitor 60 remains at 'the B3 level until time G3.At this time, the timing circuit 80 provides a ground at the terminal G3which is connected to current source 81 to render the same inoperativeto supply current to capacitor 60. vThe ground at terminal-G3 alsocompletes a path through diode 145 to the collector 146 of currentsource transistor 84a. The current through diode 145 diverts currentfrom the path through the diode 147 to the base of transistor 148, andacts to turn off transistor 148. The conduction of transistor 148 priorto time G3 has held transistor 150, 154and 155 turned off. This insuresthat the B4 voltage level established by resistors 151 and 152 from V,to ground, does not control the voltage on the capacitor 60 (or 62). Nowwhen transistor 148 turns off, transistors 150 and 154(or 155 forcapacitor 62) are rendered conducting, and are in a condition to applythe B4 potential from the'voltage divider including resistors 151 and152 to capacitor 60.

Transistor 148 when conducting also produces a voltage across diode 15.6and resistor 157, connected between the emitter of transistor 148 andground. This voltage is applied through conductor 158 to the base oftransistor 160 and acts to hold transistor 160 conduct-- ing. Thisproduces a voltage drop across resistor 163 which reverse biases theemitter-base junction of transistor 162 rendering it non-conductingfNowat time G3 when transistor 148 is turned off, the positive potential isremoved from the base of transistor 160 so that it turns off. Thisremoves the clamp applied to the emitter of transistor 162 which isconnected through resistor 163 to the regulated voltage. The base oftransistor 162 is connected to the emitter of transistor 164, the baseof which is connected to the voltage di- I vider string includingresistors 126, 127 and 128. The base of transistor 162 is also connectedto the collector of transistor 165, having its base connected acrossdiode 69 in the voltage divider string including resistors 67, 68 andtransistor 84. Transistor 165 supplies base current for transistor 162so that transistors '162 and 164 are rendered conducting, and the baseof transistor 162 is held at the potential applied thereto fromtransistor 164 connected to the voltage divider. Because of the voltagecancellation of the base-emitter junctions of transistors 164 and 162,the voltage at the emitter of transistor 162 is the same as the voltageat the base of transistor 164. This voltage and the value of resistor163 will determine the amount of conduction of transistor 162.

The conduction of transistor 162 will cause current flow through diode130 to turn on transistor 75 to complete the path through transistor 72,as previously described. Accordingly, at time G3, capacitor 60 willdischarge through transistors 72 and 75 until the voltage thereacrossreaches the B4 level. If capacitor 60 falls below the B4 level, emitterfollower transistor 154 will be rendered conducting to supply current tocapacitor 60 until the B4 voltage value is reached. Transistor 154essentially supplies the current cemanded by the collector of transistor72 and thus this flop changes, the capacitor on which the waveform hasbeen developed, capacitor 60 in the prior description, will now bedisconnected from the circuit which provides the waveform, as transistor72 will be rendered nonconducting by the differential circuit 70. Atthis same time the current source 76 will provide the operating rampacross this capacitor. The current source 76 may be as described inapplication Ser. No. 189,521 filed Oct. 15, 1971, assigned to theassignee of the present application.

During the time that the operating ramp is being developed acrosscapacitor 60, the waveform as shown in FIG. 1 will be developed acrosscapacitor 62. The operation is the same as has been described, exceptthat transistors 88, 116 and 155 which are connected to capacitor 62will now be operative to regulate the voltage on this capacitor, whiletransistors 89, 117 and 154 are inoperative. Transistors 88, 116, and155 were inoperative when the waveform was generated on capacitor 60because the voltage on capacitor 62 was at some high ramp 25 voltage,such as that shown in FIG. 1. This forces all of the base-emitterjunctions of these transistors to be reversed biased and thus rendersthem nonconducting. Also, the discharging action on capacitor 62 will bethrough transistor 73 and either of transistor or transistor 98,depending upon the particular portion of the waveform which is beingproduced. The current source 81 will be connected to 60, to provide theup ramp 16 in thewaveform.

The circuit of the invention hasbeen found to provide the voltagewaveform described with extremely high accuracy, theaccuracy beingwithin one percent I The circuit of the invention when provided as anintegrated circuit chip forms a compact and inexpensive unit. Thevoltage dividers can'be external to the chip so I that the voltagelevels can be independently set as desired. Also, the resistors 126 and163 canbe external to the chip allowing the ramps 12 and 20 of FIG. 1 toalso be-determined. External components can be provided for currentsources 81 and 76 to allow complete adjustment of every portion of thewaveform including the B levels, the slope of each ramp, andthe'breakpoints'(G1, G2, G3). By making such components exstructionhaving a reasonable number of terminals for connection to externalcomponents.

We claim:

1. A circuit for developing across a capacitor a waveform having aplurality of different voltage levels at least one of whichis greaterthan the preceding level and at least one of which is less than thepreceding level, such circuit including in combination, reference meansproviding aplurality, of reference voltages representing the differentvoltage levels of the waveform, regulator means coupled to saidreferencemeans and :to thecapacitor for selectively holding the voltagethereacross at a value-associated with one of the reference voltages,discharge circuit means connected to the capacitor and to saidjregulatormeans and adapted to be rendered operative by said' regulator means todischarge thecapacitor .and reduce thevoltage thereacross until aselected one of the voltage levels is reached, and current source meansconnected to the capacitor and adapted to operate to supply currentthereto to increase the voltage thereacross until another one of thevoltage levels is reached.

The circuit of claim 1 further including timing means coupled to saidregulator-means and to said current source means for rendering'the sameoperative in a predetermined time relation.

3. A circuit in accordance with claim 2 wherein said timing means cauessaid regulator means to control the voltage across the capacitor at afirst level in response to a first reference voltage and thereafterapplies a control potential to said regulator means to control thevoltage across the capacitor at a second level in response to a secondreference voltage.

4. A circuit in accordance with claim 2 wherein said regulator meansincludes a differential amplifier connected to the capacitor andresponsive to a voltage on the capacitor above the first voltage levelto control said discharge circuit to discharge the capacitor to thefirst voltage level, said differential amplifier being ternal, it isstillpossible to use an integrated circuit conresponsive to a firstreference voltage to hold the voltage across the capacitor at the firstvoltage level,.and

wherein said timing means deactivates said discharge circuitry to allowsaid current source to charge the capacitor so that the voltagethereacross increases to a second voltage level, said timing meanscontrolling said regulator means so that said differential amplifierresponds to a second referencevoltage and operates said dischargecircuit to prevent charge of the capacitor above the second voltagelevel so that the voltage across the capacitor is held at the secondvoltage level.

5. A circuit in accordance with claim 2 wherein said regulator meansincludes an emitter follower circuit connected between said referencemeans and the capacitor and responsive to the voltage on the capacitor,said timing means controlling said regulator means so that said emitterfollower circuit responds to a first reference voltage and actuates saiddischarge circuit means to discharge the capacitor so that the voltagethereacross decreases to the first voltage level, said emitterfollower-operating to hold the voltage across the capacitor at-saidfirst voltage level.

6. A circuit in accordance with claim 2 wherein said regulator meansinitially responds to a first reference voltage and operates saiddischagge circuit means to cause the capacitor to discharge to a firstvoltage level frelated to said first reference voltage, said timingmeans applying a first control signal to said regulator means to causethe same to operate in response to a second reference voltage and tocause said discharge circuit to discharge the 'capacitor so that thevoltage thereacross drops to a second voltage level related to saidsecond reference voltage, said timing means applying a second controlsignal to said regulator means to control said discharge circuit so.that said current source means charges the capacitor so that the voltagethereacross rises from the second voltage level toa third'voltage level,with said regulator-means being responsive to a third reference voltageto operate said discharge circuit means so that the voltage across thecapacitor'does not rise above the third voltage level,

and said timing means applyinga-third control signal to said currentsource means and to said regulator means to render said currentsourcemeans inoperative and cause said. regulator means to respond to a fourthreference potential and to operate said discharge circuit means todischarge the capacitor so that the voltage thereacross drops fromthethird voltage level to a fourth voltage level, said regulator meansacting to hold the voltage across the capacitor at each voltage level 1until a further control signal is received.

7. A circuit in accordance with claim 1 wherein said discharge circuitmeans includes first and second por-' of said regulator means respondingto a second' reference voltage to operate said second portion of saiddischarge circuit means.

8. The circuit of claim 1 wherein said current source means isselectively operated to charge the capacitor to provide a voltage rampsuperimposed on the voltage waveform thereacross, and further includingtrigger means coupled to said regulator means and to said current sourcemeans for controlling the initiation of the waveform across thecapacitor and the initiation of the voltage ramp, and means coupled tothe capacitor for providing a control in response to the superimposedvoltage across the capacitor.

g 9. A circuit in accordance with claim 8 wherein said current sourcemeans includes first and second current supply means selectivelyconnected to said capacitor means, said regulator means includes controlmeans for selectively rendering said regulator means responsive todifferent ones of said reference voltages, and further including timingmeans coupled to said regulator means and to said first current supplymeans,'said regulator means being initially responsive to afirstreference voltage and operating said discharge circuit means tocause said capacitor means to discharge to a first voltage level relatedto said first reference voltage, and wherein said timing means applies afirst control signal to said control means to' cause said regulatormeans to operate in response to a second reference voltage and to causesaid discharge circuit to 'discharge said capacitor means so that thevoltage thereacrossdrops to a second voltagelevel related to said secondreference voltage, said timing means applying a second control signaltosaid control means at a time following the first control signal tooperate said discharge circuit means so that said first current supplymeans charges said capacitor means so that the voltage thereacross risesfrom the second voltage level to a third voltage level, said regulatormeans being rendered responsive to a third reference voltage to operatesaid discharge circuit means so that the voltage across said capacitormeans does not rise above the third voltage level, and

said timing means applying a third control signal to said first currentsupply means and to said control means at a time followingthe secondcontrol signal to render said first current supply means inoperative andcause said regulator means to respond to a fourth reference potentialand to operate said discharge circuit means to discharge said capacitormeans so that the voltage thereacross drops from the third voltage levelto a fourth voltage level, with the waveform across the capacitorincluding said first, second, third and fourth voltage levels, saidtrigger means interrupting the waveform and causing said second currentsupply means to charge the capacitor to provide the voltage rampsuperimposed on the voltage waveform across the capacitor at the time ofinterruption.

10. A circuit in accordance with claim 9 wherein said regulator meansincludes a differential amplifier connected to said capacitor means andsaid discharge circuit means includes first and second portions, saiddifferential amplifier being responsive to a voltage on said capacitormeans above the first voltage level to control said first portion ofsaid discharge circuit means to discharge said capacitor means to thefirst voltage level, said differential amplifier being responsive to afirst reference voltage to hold the voltage across said capacitor meansat the first voltage level, wherein said control means responds to saidfirst control signal from said timing means to cause said regulatormeans to control said second portion of said discharge circuit means todischarge said capacitor means so that the voltage thereacross dropsfrom said first voltage level to said second voltage level, wherein saidcontrol means responds to said second control signal from said timingmeans to actuate said regulator means so that said differentialamplifier responds to said third reference voltage and operates saidfirst portion of said discharge circuit means to prevent further chargeof said capacitor means by said first current supply means so that thevoltage thereacross does not rise above the third voltage level, andwherein said control means responds to said third control signal fromsaid timing means to cause said first current supply means to beinoperative and to cause said regulator means to-control said secondportion of said discharge circuit means to discharge said capacitormeans so that the voltage thereacross drops from said third voltagelevel to said fourth voltagelevel.

11. A circuit for producing a predetermined voltage wave having aplurality of different voltage levels, at

. least one of which is greater than the preceding level and at leastone of which is less than the preceding level, such circuit including incombination, capacitor means, reference means providing a plurality ofreference voltage presenting the different voltage levels of thevoltagewave, regulator means coupled to said reference voltage'and tosaid capacitor means for selectively'holdingthe voltage thereacross at avalue associated with one of the reference voltages, current sourcemeans connected to said capacitor means to supply current to saidcapacitor means to charge the same, and discharge circuit meansconnected to said capacitor means and to said regulator means andadapted to be rendered operative by said regulator means to dischargesaid capacitor means and to reduce the voltage thereacross until aselected one of said different voltage levels is reached, said dischargecircuit means being controlled so that said current source means chargessaid capacitor means to increase the voltage thereacross until anotherone of the voltage levels, which is greater than the preceding level, isreached.

12. The circuit of claim 11 wherein said regulator means includescontrol means for selectively rendering the same responsive to differentones of said reference voltages, and said regulator means is operativeto hold the voltage across said capacitor means at a value related toone of said reference voltages until said control means operates torender said regulator means responsive to a different reference voltage.

13. A circuit in accordance with claim 11 wherein said regulator meansincludes control means for selectively rendering the same responsive todifferent ones of said reference voltage, said regulator means beinginitially responsive to a first reference voltage and operating saiddischarge circuit means to cause said capacitor means to discharge to afirst voltage level related to said first reference voltage, and furtherincluding timing means coupled to said control means and to said currentsource means, said timing means applying a first control signal to saidcontrol means to cause said regulator means to operate in response to asecond reference voltage and to cause said discharge circuit means todischarge said capacitor means so that the voltage thereacross drops toa second voltage level related to said second reference voltage, saidtiming reference voltage to operate saiddischarge circuit means so thatthe voltage across said capacitor means does not rise above the thirdvoltage-level, and said tim-' ing meansapplying a third control signalto said current source means and to. said regulator means to render saidcurrent source inoperative, and to cause said regulator means to respondto a fourth reference potential and to operate said discharge circuitmeans to discharge said capacitor means so that the voltage thereacrossdrops from the third voltage level to a fourth voltage level. I

14. A circuit in accordance with claim 13 wherein I said dischargecircuit means includes a first portion which causes said capacitor meansto discharge to said first voltage level and which operates" to preventthe voltage across-said capacitor means from rising above said thirdvoltage level, and a second portion which causes saidca'pacitor means todischarge so that the to said second voltage level and to discharge sothat the voltage thereacross drops from said third voltage level to saidfourth voltage level.

25 voltage thereacross drops from. said first voltage level voltageonsaid capacitor means above the first voltage level to control saiddischarge circuit means to discharge said capacitor means to the firstvoltage level, said differential amplifier being responsive to a firstreference voltage to hold the voltage across said capacitor means at thefirst voltage level, and wherein said second control signal from saidtiming means actuates said regulator means so that said differentialamplifier responds to said third reference voltage and operates saiddisharge circuit means to prevent charge of said capacitor means by saidcurrent source means so that the voltage thereacross rises above thethird voltage level, whereby the voltage across said capacitor means isheld at the third voltage level.

16. The circuit of claim 13 wherein said capacito means includes firstand second capacitors and wherein said regulator means, said dischargecircuit means and said current source means are selectively coupled tosaid first capacitor to provide the voltage wave thereacross during afirst'cycle, and are connected to said second capacitor to provide thevoltage wave thereacross during a secondv cycle;

17. A circuit'in accordance with claim 16 further including rampcurrent. means and means for selectively couplingsaid ramp current:means to said first and second capacitors .toprovide a ramp'voltagesuperimposed on the voltage wave across said first capacitor during thetsecond cycle, and to provide a ramp voltage superimposed on the voltage'wave across said second capacitor during a third' cycle.

1. A circuit for developing across a capacitor a waveform having aplurality of different voltage levels at least one of which is greaterthan the preceding level and at least one of which is less than thepreceding level, such circuit including in combination, reference meansproviding a plurality of reference voltages representing the differentvoltage levels of the waveform, regulator means coupled to saidreference means and to the capacitor for selectively holding the voltagethereacross at a value associated with one of the reference voltages,discharge circuit means connected to the capacitor and to said regulatormeans and adapted to be rendered operative by said regulator means todischarge the capacitor and reduce the voltage thereacross until aselected one of the voltage levels is reached, and current source meansconnected to the capacitor and adapted to operate to supply currentthereto to increase the voltage thereacross until another one of thevoltage levels is reached.
 2. The circuit of claim 1 further includingtiming means coupled to said regulator means and to said current sourcemeans for rendering the same operative in a predetermined time relation.3. A circuit in accordance with claim 2 wherein said timing means cauessaid regulator means to control the voltage across the capacitor at afirst level in response to a first reference voltage and thereafterapplies a control potential to said regulator means to control thevoltage across the capacitor at a second level in response to a secondreference voltage.
 4. A circuit in accordance with claim 2 wherein saidregulator means includes a differential amplifier connected to thecapacitor and responsive to a voltage on the capacitor above the firstvoltage level to control said discharge circuit to discharge thecapacitor to the first voltage level, said differential amplifier beingresponsive to a first reference voltage to hold the voltage across thecapacitor at the first voltage level, and wherein said timing meansdeactivates said discharge circuitry to allow said current source tocharge the capacitor so that the voltage thereacross increases to asecond voltage level, said timing means controlling said regulator meansso that said differential amplifier responds to a second referencevoltage and operates said discharge circuit to prevent charge of thecApacitor above the second voltage level so that the voltage across thecapacitor is held at the second voltage level.
 5. A circuit inaccordance with claim 2 wherein said regulator means includes an emitterfollower circuit connected between said reference means and thecapacitor and responsive to the voltage on the capacitor, said timingmeans controlling said regulator means so that said emitter followercircuit responds to a first reference voltage and actuates saiddischarge circuit means to discharge the capacitor so that the voltagethereacross decreases to the first voltage level, said emitter followeroperating to hold the voltage across the capacitor at said first voltagelevel.
 6. A circuit in accordance with claim 2 wherein said regulatormeans initially responds to a first reference voltage and operates saiddischagge circuit means to cause the capacitor to discharge to a firstvoltage level related to said first reference voltage, said timing meansapplying a first control signal to said regulator means to cause thesame to operate in response to a second reference voltage and to causesaid discharge circuit to discharge the capacitor so that the voltagethereacross drops to a second voltage level related to said secondreference voltage, said timing means applying a second control signal tosaid regulator means to control said discharge circuit so that saidcurrent source means charges the capacitor so that the voltagethereacross rises from the second voltage level to a third voltagelevel, with said regulator means being responsive to a third referencevoltage to operate said discharge circuit means so that the voltageacross the capacitor does not rise above the third voltage level, andsaid timing means applying a third control signal to said current sourcemeans and to said regulator means to render said current source meansinoperative and cause said regulator means to respond to a fourthreference potential and to operate said discharge circuit means todischarge the capacitor so that the voltage thereacross drops from thethird voltage level to a fourth voltage level, said regulator meansacting to hold the voltage across the capacitor at each voltage leveluntil a further control signal is received.
 7. A circuit in accordancewith claim 1 wherein said discharge circuit means includes first andsecond portions selectively coupled to the capacitor for discharging thesame, and said regulator means includes first and second portionscoupled respectively to said first and second portions of said dischargecircuit means, said first portion of said regulator means responding toa first reference voltage to operate said first portion of saiddischarge circuit means, and said second portion of said regulator meansresponding to a second reference voltage to operate said second portionof said discharge circuit means.
 8. The circuit of claim 1 wherein saidcurrent source means is selectively operated to charge the capacitor toprovide a voltage ramp superimposed on the voltage waveform thereacross,and further including trigger means coupled to said regulator means andto said current source means for controlling the initiation of thewaveform across the capacitor and the initiation of the voltage ramp,and means coupled to the capacitor for providing a control in responseto the superimposed voltage across the capacitor.
 9. A circuit inaccordance with claim 8 wherein said current source means includes firstand second current supply means selectively connected to said capacitormeans, said regulator means includes control means for selectivelyrendering said regulator means responsive to different ones of saidreference voltages, and further including timing means coupled to saidregulator means and to said first current supply means, said regulatormeans being initially responsive to a first reference voltage andoperating said discharge circuit means to cause said capacitor means todischarge to a first voltage level related to said First referencevoltage, and wherein said timing means applies a first control signal tosaid control means to cause said regulator means to operate in responseto a second reference voltage and to cause said discharge circuit todischarge said capacitor means so that the voltage thereacross drops toa second voltage level related to said second reference voltage, saidtiming means applying a second control signal to said control means at atime following the first control signal to operate said dischargecircuit means so that said first current supply means charges saidcapacitor means so that the voltage thereacross rises from the secondvoltage level to a third voltage level, said regulator means beingrendered responsive to a third reference voltage to operate saiddischarge circuit means so that the voltage across said capacitor meansdoes not rise above the third voltage level, and said timing meansapplying a third control signal to said first current supply means andto said control means at a time following the second control signal torender said first current supply means inoperative and cause saidregulator means to respond to a fourth reference potential and tooperate said discharge circuit means to discharge said capacitor meansso that the voltage thereacross drops from the third voltage level to afourth voltage level, with the waveform across the capacitor includingsaid first, second, third and fourth voltage levels, said trigger meansinterrupting the waveform and causing said second current supply meansto charge the capacitor to provide the voltage ramp superimposed on thevoltage waveform across the capacitor at the time of interruption.
 10. Acircuit in accordance with claim 9 wherein said regulator means includesa differential amplifier connected to said capacitor means and saiddischarge circuit means includes first and second portions, saiddifferential amplifier being responsive to a voltage on said capacitormeans above the first voltage level to control said first portion ofsaid discharge circuit means to discharge said capacitor means to thefirst voltage level, said differential amplifier being responsive to afirst reference voltage to hold the voltage across said capacitor meansat the first voltage level, wherein said control means responds to saidfirst control signal from said timing means to cause said regulatormeans to control said second portion of said discharge circuit means todischarge said capacitor means so that the voltage thereacross dropsfrom said first voltage level to said second voltage level, wherein saidcontrol means responds to said second control signal from said timingmeans to actuate said regulator means so that said differentialamplifier responds to said third reference voltage and operates saidfirst portion of said discharge circuit means to prevent further chargeof said capacitor means by said first current supply means so that thevoltage thereacross does not rise above the third voltage level, andwherein said control means responds to said third control signal fromsaid timing means to cause said first current supply means to beinoperative and to cause said regulator means to control said secondportion of said discharge circuit means to discharge said capacitormeans so that the voltage thereacross drops from said third voltagelevel to said fourth voltage level.
 11. A circuit for producing apredetermined voltage wave having a plurality of different voltagelevels, at least one of which is greater than the preceding level and atleast one of which is less than the preceding level, such circuitincluding in combination, capacitor means, reference means providing aplurality of reference voltage presenting the different voltage levelsof the voltage wave, regulator means coupled to said reference voltageand to said capacitor means for selectively holding the voltagethereacross at a value associated with one of the reference voltages,current source means connected to said capacitor means to supPly currentto said capacitor means to charge the same, and discharge circuit meansconnected to said capacitor means and to said regulator means andadapted to be rendered operative by said regulator means to dischargesaid capacitor means and to reduce the voltage thereacross until aselected one of said different voltage levels is reached, said dischargecircuit means being controlled so that said current source means chargessaid capacitor means to increase the voltage thereacross until anotherone of the voltage levels, which is greater than the preceding level, isreached.
 12. The circuit of claim 11 wherein said regulator meansincludes control means for selectively rendering the same responsive todifferent ones of said reference voltages, and said regulator means isoperative to hold the voltage across said capacitor means at a valuerelated to one of said reference voltages until said control meansoperates to render said regulator means responsive to a differentreference voltage.
 13. A circuit in accordance with claim 11 whereinsaid regulator means includes control means for selectively renderingthe same responsive to different ones of said reference voltage, saidregulator means being initially responsive to a first reference voltageand operating said discharge circuit means to cause said capacitor meansto discharge to a first voltage level related to said first referencevoltage, and further including timing means coupled to said controlmeans and to said current source means, said timing means applying afirst control signal to said control means to cause said regulator meansto operate in response to a second reference voltage and to cause saiddischarge circuit means to discharge said capacitor means so that thevoltage thereacross drops to a second voltage level related to saidsecond reference voltage, said timing means applying a second controlsignal to said control means to control said discharge circuit means sothat said current source means charges said capacitor means so that thevoltage thereacross rises from the second voltage level to a thirdvoltage level, said regulator means being rendered responsive to a thirdreference voltage to operate said discharge circuit means so that thevoltage across said capacitor means does not rise above the thirdvoltage level, and said timing means applying a third control signal tosaid current source means and to said regulator means to render saidcurrent source inoperative, and to cause said regulator means to respondto a fourth reference potential and to operate said discharge circuitmeans to discharge said capacitor means so that the voltage thereacrossdrops from the third voltage level to a fourth voltage level.
 14. Acircuit in accordance with claim 13 wherein said discharge circuit meansincludes a first portion which causes said capacitor means to dischargeto said first voltage level and which operates to prevent the voltageacross said capacitor means from rising above said third voltage level,and a second portion which causes said capacitor means to discharge sothat the voltage thereacross drops from said first voltage level to saidsecond voltage level and to discharge so that the voltage thereacrossdrops from said third voltage level to said fourth voltage level.
 15. Acircuit in accordance with claim 13 wherein said regulator meansincludes a differential amplifier connected to said capacitor means andresponsive to a voltage on said capacitor means above the first voltagelevel to control said discharge circuit means to discharge saidcapacitor means to the first voltage level, said differential amplifierbeing responsive to a first reference voltage to hold the voltage acrosssaid capacitor means at the first voltage level, and wherein said secondcontrol signal from said timing means actuates said regulator means sothat said differential amplifier responds to said third referencevoltage and operates said disharge circuit means to prevent charge ofsaid capacitor means By said current source means so that the voltagethereacross rises above the third voltage level, whereby the voltageacross said capacitor means is held at the third voltage level.
 16. Thecircuit of claim 13 wherein said capacitor means includes first andsecond capacitors and wherein said regulator means, said dischargecircuit means and said current source means are selectively coupled tosaid first capacitor to provide the voltage wave thereacross during afirst cycle, and are connected to said second capacitor to provide thevoltage wave thereacross during a second cycle.
 17. A circuit inaccordance with claim 16 further including ramp current means and meansfor selectively coupling said ramp current means to said first andsecond capacitors to provide a ramp voltage superimposed on the voltagewave across said first capacitor during the second cycle, and to providea ramp voltage superimposed on the voltage wave across said secondcapacitor during a third cycle.